Part of the REV4 revision of the WonderMCA board objective was to introduce 16Bit data Bus instead of 8Bit.All the PS\/2 MCA Bus are able to handle 16Bits data slave along with 24Bits address lines. The expected outcome is to double the MEM & IO bandwidth and thus increase the native disk transfer.<\/p>\n\n\n\n
The new board revision provides now 2 SN74CB3T3245DWR to cover DO-15 data lines, following the same multiplexing logic to the RP2350.<\/p>\n\n\n\n
When D_OE signal is asserted (LOW), then A_OE is HIGH and the 2 SN74CB3T3245DWR are active to read or write data on the MCA bus according the cycle type (MEMR,MEMW,IOR,IOW)<\/p>\n\n\n\n
Reading carefully the MCA sepcification the following new signals needs to be handle both by the CPLD and by the RP2350<\/p>\n\n\n\n
\/CD_DS_16 follow exactly the same tricky timing constraint and need to be asserted as soon as a valid MIO and unlatched address is present on the MCA Bus. It means that the CPLD needs to manage the right combinaition to assert this line according the address scope on the bus (D0000+D4000). CD_DS_16 need to be deasserted as soon as the address scope is not valid anymore on the bus. This mecanism is different from CHRDY and will require special equation on the CPLD.<\/p>\n\n\n\n
As a first step, 16 bit data transfer will be enable for MEMR & MEMW cycle and we will extend it to IOR and IOW afterwards.<\/p>\n\n\n\n
The IBM specification (HITRA02), provdides on page 53 the data steering mecanism, and it requires to spend sometimes to really understand what kind of case to be handled<\/p>\n\n\n\n
These are the 4 case provided by the IBM specs according the A0,A1 and \/SBHE for a single byte A,B,C,D.<\/p>\n\n\n\n First case is and even Address with A0=0 and \/SBHE not asserted, it is like a classic 8 bit transfer the High data bank (D8-D15) is ignored (should be).<\/p>\n\n\n\n Second case is an odd Address with A0=1 and \/SBHE asserted, still single bytes however it has to be provided on the High Address bank… It seems a bit wired<\/p>\n\n\n\n The 3rd and 4th case are the same but with Address A1.<\/p>\n\n\n\n Now for a 2 Bytes transfer:<\/p>\n\n\n\n It is pretty much the same approach,<\/p>\n\n\n\n Assembling Single (A,B) and 2 Bytes (AB) transfer these are the case to be implemented:<\/p>\n\n\n\n if you look more closely, there is one missing case that is<\/p>\n\n\n\n And the specification note 6 is quite explicit: “Combinations of \/SBHE, A1, Ao not shown in the table are not permitted”<\/p>\n\n\n\n For MEMR and MEMW we will focus only on the 3 defined and allowed case, and of course build the test tool to validate that any chassis will not try to perform the last not defined case.<\/p>\n\n\n\n Going further down to the design and considering the case C1,C2,C3 for MEMR and MEMW cycles. Assuming that CD_DS_16 will always asserted for the valid address scope D000 & D4000 range, the RP2350 core1 memory fast path needs to be adjusted.<\/p>\n\n\n\n MEMR cycles are the chassis reading memory, and the WonderMCA needs to provides on the bus valid data lines signals during the \/CMD data window. We would manage the memory path this way<\/p>\n\n\n\n note: DPRAM is the shared address space shared between the chassis and the WonderMCA<\/p>\n\n\n\n For C1 and C2, the WonderMCA provides the data on the bank This is pretty cool because it adds 0 cycle (almost) to the current very tight ASM window on the core1. It means that last address line is ignored for the MEMR path.<\/p>\n\n\n\n on Core1, the DPRAM offset is It seems to be different for MEMW as we need to be careful on the data bank based on A0 and \/SBHE<\/p>\n\n\n\n for MEMW cycles, it is different because we need to take care of the A0 & SBHE combination to write the right data to DPRAM.<\/p>\n\n\n\n Unlike the read path \u2014 where we could be lazy and drive both banks blindly, letting the chassis pick the one it cares about \u2014 on a write we<\/strong> are the one capturing the bus, so we have to steer each incoming byte to the correct DPRAM offset. Drop a byte in the wrong bank, or write a bank the chassis never actually drove, and you silently corrupt the neighbouring byte in DPRAM.<\/p>\n\n\n\n Staring at the IBM steering table long enough, it collapses to one simple rule:<\/p>\n\n\n\n So with which boils down to two conditions:<\/p>\n\n\n\n The low bank is captured whenever A0=0 (C1 and C3); the high bank whenever \/SBHE is asserted (C2 and C3). The odd single-byte case C2<\/strong> is the one that always catches you out: A0=1, so the low store is suppressed, and the lone byte rides in on the high<\/strong> half of the bus to land at On the Core1 fast path this is a touch more expensive than the read side. Instead of a single blind store we now:<\/p>\n\n\n\n Worst case (C3, a full word) that is two stores and a branch or two \u2014 still comfortably inside the \/CMD data window, but no longer “free” like MEMR. The read path stayed elegant; the write path had to earn its 16 bits.<\/p>\n\n\n\n For REV4 the plan is to land 16-bit MEMR\/MEMW<\/strong> first, on the three legal cases C1\/C2\/C3 \u2014 and, just as important, to ship a little test tool that hammers every A0 \/\/ \/SBHE combination and screams if a chassis ever tries the forbidden Once MEMR\/MEMW are solid and \/CD_DS_16 is asserting cleanly over the D0000-D4000 window, IOR\/IOW<\/strong> in 16-bit is the next bank to open \u2014 same steering logic, same tight timing, twice the I\/O bandwidth. And with both memory and I\/O running 16 bits wide, the native disk path finally gets the doubling this whole revision was chasing.<\/p>\n\n\n\n <\/p>\n","protected":false},"excerpt":{"rendered":" Part of the REV4 revision of the WonderMCA board objective was to introduce 16Bit data Bus instead of 8Bit.All the PS\/2 MCA Bus are able to handle 16Bits data slave along with 24Bits address lines. The expected outcome is to double the MEM & IO bandwidth and thus increase the native disk transfer. The new […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center 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A1<\/th> A0<\/th> D8-D15<\/th> D0-D7<\/th><\/tr><\/thead> 1<\/td> 0<\/td> 0<\/td> –<\/td> A<\/td><\/tr> 0<\/td> 0<\/td> 1<\/td> B<\/td> –<\/td><\/tr> 1<\/td> 1<\/td> 0<\/td> –<\/td> C<\/td><\/tr> 0<\/td> 0<\/td> 1<\/td> D<\/td> –<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n \/SBHE<\/th> A1<\/th> A0<\/th> D8-D15<\/th> D0-D7<\/th><\/tr><\/thead> 0<\/td> 0<\/td> 0<\/td> B<\/td> A<\/td><\/tr> 0<\/td> 1<\/td> 0<\/td> D<\/td> C<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n Case #<\/th> \/SBHE<\/th> A1<\/th> A0<\/th> D8-D15<\/th> D0-D7<\/th><\/tr><\/thead> C1<\/td> 1<\/td> 0<\/td> 0<\/td> –<\/td> A<\/td><\/tr> C2<\/td> 0<\/td> 0<\/td> 1<\/td> B<\/td> –<\/td><\/tr> C3<\/td> 0<\/td> 0<\/td> 0<\/td> B<\/td> A<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n \/SBHE<\/th> A1<\/th> A0<\/th> D8-D15<\/th> D0-D7<\/th><\/tr><\/thead> 1<\/td> 0<\/td> 1<\/td> –<\/td> A<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n Case #<\/th> \/SBHE<\/th> A1<\/th> A0<\/th> D8-D15<\/th> D0-D7<\/th><\/tr><\/thead> C1<\/td> 1<\/td> 0<\/td> 0<\/td> DPRAM+1 (ignored)<\/td> DPRAM<\/td><\/tr> C2<\/td> 0<\/td> 0<\/td> 1<\/td> DPRAM+1<\/td> DPRAM (ignored)<\/td><\/tr> C3<\/td> 0<\/td> 0<\/td> 0<\/td> DPRAM+1<\/td> DPRAM<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n MCA Addr & window_mask<\/code> with the low bit forced to 0 (the even-aligned base of the pair) \u2014 the read path ignores A0 and always presents DPRAM<\/code> on D0-D7 and DPRAM+1<\/code> on D8-D15, letting the chassis take whichever bank it actually asked for.<\/p>\n\n\n\n\n
base = (MCA Addr & window_mask) & ~1<\/code> (the even-aligned offset), the two bank writes are completely independent:<\/p>\n\n\n\nCase #<\/th> \/SBHE<\/th> A1<\/th> A0<\/th> write D0-D7 -><\/th> write D8-D15 -><\/th><\/tr><\/thead> C1<\/td> 1<\/td> 0<\/td> 0<\/td> DPRAM[base]<\/td> \u2014 (not driven)<\/td><\/tr> C2<\/td> 0<\/td> 0<\/td> 1<\/td> \u2014 (not driven)<\/td> DPRAM[base+1]<\/td><\/tr> C3<\/td> 0<\/td> 0<\/td> 0<\/td> DPRAM[base]<\/td> DPRAM[base+1]<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n WE_low = (A0 == 0) -> DPRAM[base] = D0-D7\nWE_high = (\/SBHE asserted) -> DPRAM[base+1] = D8-D15\n<\/code><\/pre>\n\n\n\nbase+1<\/code> \u2014 exactly the odd offset the chassis is addressing. It looks weird on paper, but it is the same odd-byte-on-the-high-bank trick every 16-bit ISA\/MCA slave plays.<\/p>\n\n\n\n\n
Where this leaves us<\/h2>\n\n\n\n
\/SBHE=1, A0=1<\/code> case that note 6 swears can’t happen. Trust, but verify: the whole reason WonderMCA works across the PS\/2 zoo is that “the spec says X” and “this particular planar actually does X” are not always the same sentence.<\/p>\n\n\n\n