The card that vanished from setup

WonderMCA had been enumerating cleanly across the PS/2 matrix for weeks. POST passed, the option ROM checksummed, the adapter ID showed up in the reference-diskette setup. Then I sat down at the IBM PS/2 Model 57 — the 8557, a 386SX desktop — booted it, and the card was simply not there. No adapter, no slot, nothing. POST didn’t even complain; from the chassis’s point of view there was no WonderMCA in the bus at all.

That’s a particular kind of frustrating. A crash gives you a code. A disappearance gives you nothing. The card was clearly alive — the screenpad lit up, Core 0 was running, the UART banner printed — but the one thing it had to do during the first second of POST, answer the POS scan, it wasn’t doing.

What the card is supposed to do

A quick … Read the rest

A driver that “shouldn’t” work

For most of WonderMCA’s development the chassis matrix looked encouraging. The card came up clean on the IBM PS/2 Model 8550Z, on the 8555, on the 8556, on the 8557. POST passed, the option ROM checksum was correct, the screenpad lit up, the floppy emulator mounted images, the NE2000 tunnelled traffic over W5500. By early May 2026 four 286-class & 386 PS/2 boxes were green across the matrix.

Then I plugged the same card into a Model 8570 — the 25 MHz 386DX desktop — and got:

D0000  114

POST 114. The chassis BIOS had scanned for option ROMs in the C000–DFFF region, found WonderMCA’s 0x55 0xAA signature at segment D000, summed the declared 16 KB, and the modulo-256 result wasn’t zero. From the chassis’s point of view the option ROM was corrupt.

But it wasn’t corrupt. The 16 KB ROM image is built by … Read the rest

After several weeks of design work, I finally received the first WonderMCA prototype PCB. I’ve been using JLCPCB for months now, and they consistently deliver: the quality is excellent and the path from design to physical board is remarkably smooth.

The First Milestone: Four Basic Transfers

My first milestone was to get the WonderMCA (WM) handling the four fundamental MCA bus transfer types:

• MEMR — Memory Read
• MEMW — Memory Write
• IOR — I/O Read
• IOW — I/O Write

Per the MCA specification, these transfers are encoded on the bus as follows:

I started my experimentation on the PS/2 model 55 for no specific reason, and it was a good choice to start and I discover also very quickly the cliff in front of me.

Memory cycles (MEMR/MEMW) must complete … Read the rest