WonderMCA – Adding data bit on the BUS
Part of the REV4 revision of the WonderMCA board objective was to introduce 16Bit data Bus instead of 8Bit.All the PS/2 MCA Bus are able to handle 16Bits data slave along with 24Bits address lines. The expected outcome is to double the MEM & IO bandwidth and thus increase the native disk transfer.
The new board revision provides now 2 SN74CB3T3245DWR to cover DO-15 data lines, following the same multiplexing logic to the RP2350.
When D_OE signal is asserted (LOW), then A_OE is HIGH and the 2 SN74CB3T3245DWR are active to read or write data on the MCA bus according the cycle type (MEMR,MEMW,IOR,IOW)
Reading carefully the MCA sepcification the following new signals needs to be handle both by the CPLD and by the RP2350
- /CD_DS_16n: This signal is an active LOW signal (Totem Pole), per MCA slot, slave driven, that defines when a slave is able to perform a





