Wonder MCA part 2 – MEM & IO path working
After several weeks of design work, I finally received the first WonderMCA prototype PCB. I’ve been using JLCPCB for months now, and they consistently deliver: the quality is excellent and the path from design to physical board is remarkably smooth.
The First Milestone: Four Basic Transfers
My first milestone was to get the WonderMCA (WM) handling the four fundamental MCA bus transfer types:
- MEMR — Memory Read
- MEMW — Memory Write
- IOR — I/O Read
- IOW — I/O Write
Per the MCA specification, these transfers are encoded on the bus as follows:
| Transfer | M/IO | S0 | S1 |
|---|---|---|---|
| MEMR | 1 | 1 | 0 |
| MEMW | 1 | 0 | 1 |
| IOR | 0 | 1 | 0 |
| IOW | 0 | 0 | 1 |
I started my experimentation on the PS/2 model 55 for no specific reason, and it was a good choice to start and I discover also very quickly the cliff in front of me.
Memory cycles (MEMR/MEMW) must complete … Read the rest