July 2026

On this project, I have so far made 2 prototype versions of the PCB, the REV2 and the REV5. The REV2 was a real draft with no CPLD to manage the MCA bus constraints, and it was a good base with all the MCA signals available on PIN Header to prototype what was supposed to be a solid version (REV5). The PCB Revision 5 is using an ATF1508 in PLCC84 format, and was supposed to be working smoothly but it was clearly not the case.

I made several mistakes on the Rev5:

• JLCPCB 10K resistors wrong 0603 reference giving 1K8 instead of 10K,
• TC2050 CPLD upload connector missing +5V from the board (as buried in the programmer reference document)
• Wrong footprint on the LDO (Power supply) of the DAC circuit,

All these should be fix with the REV8 of the board… But it is not the main issue of the … Read the rest

Part of the REV4 revision of the WonderMCA board objective was to introduce 16Bit data Bus instead of 8Bit.All the PS/2 MCA Bus are able to handle 16Bits data slave along with 24Bits address lines. The expected outcome is to double the MEM & IO bandwidth and thus increase the native disk transfer.

The new board revision provides now 2 SN74CB3T3245DWR to cover DO-15 data lines, following the same multiplexing logic to the RP2350.

When D_OE signal is asserted (LOW), then A_OE is HIGH and the 2 SN74CB3T3245DWR are active to read or write data on the MCA bus according the cycle type (MEMR,MEMW,IOR,IOW)

Reading carefully the MCA sepcification the following new signals needs to be handle both by the CPLD and by the RP2350

• /CD_DS_16n: This signal is an active LOW signal (Totem Pole), per MCA slot, slave driven, that defines when a slave is able to perform a

… Read the rest